1. Field of the Invention
The present invention relates to a method and device for preserving a pass bias inputted to a word line during the read and program operations of a NAND-type flash memory.
2. Discussion of Related Art
In general, a flash memory is a semiconductor memory showing low power consumption and maintaining stored information even when power is off. That is, the flash memory is a non-volatile memory constantly supplied with power. Differently from the DRAM, the flash memory preserves the stored information when power is off, and easily inputs/outputs the information. Accordingly, the flash memory has been widely used for a digital TV, digital camcorder, digital camera, cellular phone, PDA, game machine, MP3 player, etc.
The flash memory is divided into a NAND-type flash memory having a large memory capacity and a NOR-type flash memory having a high processing speed. The NAND-type flash memory which attains high integration and has a replaceable hand disk is mostly used to store high integration voices or images. Here, the NAND-type flash memory includes a bit line operated as an I/O terminal, a string formed by connecting a plurality of memory cell transistors in series between the bit line and a ground line, and a memory cell array having a predetermined group of the string. A control voltage is supplied to a gate of the memory cell transistor. The operation of the NAND-type flash memory will now be explained.
Generally, the write or program operation of the NAND-type flash memory cell is performed by supplying 20V to a control gate and 0V to a P well. That is, the program operation of the NAND-type flash memory cell is performed by generating Fowler-Nordheim tunneling (F-N tunneling) between a floating gate and a semiconductor substrate, by grounding a source or drain region of the memory cell and a bulk region of the substrate, and supplying a positive high voltage (program voltage; Vpp, for example, 21V) to the control gate. In the F-N tunneling, electrons in the bulk region are accumulated in the floating gate by an electric field of the high voltage Vpp supplied to the control gate, thereby increasing a threshold voltage of the memory cell. Here, the electrons are injected from the front surface of a channel to the floating gate, and the threshold value of the memory cell is about 4 to 5V. In order to write ‘0’ data, 0V is supplied to a drain voltage.
The read operation of the NAND-type flash memory cell is performed by precharging 5V to the drain, determining whether a cell current flows on the basis of a positive or negative value of the threshold voltage of the memory cell by setting the control gate in 0V, and reading ‘1’ or ‘0’ as a drain voltage value according to the determination result.
The erase operation of the NAND-type flash memory cell is performed by supplying 0V to the control gate and a high voltage of about 20V to the P well. As a result, an F-N tunneling current is generated in a gate oxide film, and the electrons flow from the floating gate to the silicon substrate. Here, the electrons are discharged from the floating gate to the front surface of the channel, and the threshold value of the memory cell becomes about −3. The F-N current is represented by the following formula:J=AE2 exp(−B/E)
J denotes a current, E denotes an electric field, and A and B are constants. This current shows high electric field dependency and low temperature dependency.
As described above, the erase operation is simultaneously performed in sector units sharing the bulk region, by generating the F-N tunneling by supplying a very low voltage (for example, 0V) to the control gate and a high voltage (for example, 20V) to the bulk region. The F-N tunneling enables the flash memory cells to have about −2V of erase threshold voltage distribution, by discharging the electrons accumulated in the floating gate to the source region. The cell having an increased threshold voltage by the program operation seems to be off because the current is prevented from flowing from the drain region to the source region during the read operation. The cell having a decreased threshold voltage by the erase operation seems to be on because the current flows from the drain region to the source region.
The excess erase and excess program operations of the NAND-type flash memory cell result from that the F-N current is sensitive to the electric field in exponential function and that a program and erase speed has different values in each cell due to variations of a capacity coupling ratio, Vcc and temperature by process variables. As a result, threshold value distribution by the excessively-erased cell increases a string current, but threshold value distribution by the excessively-programmed cell sharply reduces the string current, to generate read fail in the whole string. Accordingly, it is very important to reduce the excess program operation in the NAND-type flash memory.
On the other hand, the string comprised of the flash memory cell is formed in block units. For example, the precharge operation of the NAND-type flash memory including 512 blocks is performed by precharging word lines of 64 blocks and discharging word lines of the other blocks. The word line precharge operation of each block is performed by a precharge circuit. The precharge circuit is controlled by a word line precharge control circuit, and the precharge control circuit is disposed in each memory block.
The conventional NAND-type flash memory precharges VPP potential to, for example, 64 block word lines according to the group access control signal, discharges the precharged voltage from the non-selected word lines, and performs the program or read operation on specific cells of the selected word lines.
However, the 64 block switching devices must be enabled or disabled according to the group access control signal, which increases a switching time. Therefore, the conventional NAND-type flash memory may not discharge the block word lines in a desired time, or may form a undesired current path from the selected word lines to the ground.
Namely, when the program precharge signal has a high level, the switching devices of the precharge circuit are closed by the group access control signal, only the selected word lines are opened by combinations of the block select addresses X-Address, and the other word lines are discharged through the discharge circuit. In the program precharge operation, the block word line side has gate loading to one word line in one block, but the group access signal side has loading in minimum 64 blocks. Accordingly, time mismatching occurs in the program or read operation of the flash memory by the precharge operation of the specific word line.
In the conventional art, the group access control signal is disabled late, and thus a pass bias of the selected word line is discharged. In order to solve unwanted time mismatching, the group access control signal can control only one block, which increases the group access signal generation circuit in each block. As a result, a chip size is seriously increased. In this case, if the program precharge signal inputted to the word line precharge circuit block is corrected by using a delay, the program precharge signal requires the delay time over 100 ns (read) or 500 ns (program). Therefore, a specific delay circuit is necessary to give the delay time, which also increases the chip size.